1. Field of the Invention
This invention relates to the field of switched-capacitor, differential amplifiers.
2. Background Art
Computer systems utilizing disk drives for memory storage contain an assembly of electrical and mechanical components known as the head/disk assembly. Within this assembly, one or more disks are situated on a spindle to provide disk rotation.
At least one recording head is positioned above each data surface of each disk to read and write data. The recording heads are attached to a positioning apparatus (servo system) which provides for radial or angular movement across the surfaces of the disks. This apparatus is responsible for positioning the heads over the desired tracks on the disks.
A servo motor, such as a voice coil motor, having a primarily inductive impedance, is attached to the positioning means to control the radial movement of the heads in response to a control current received from the disk drive servo system. The servo motor responds to servo position error signals obtained from the disk surface to modify the motor current and, thus, modify the position of the recording heads.
It is sometimes desirable to be able to sense the amount of electrical current flowing through the servo motor so that the current value can be implemented in a feedback loop with the motor control circuitry within the servo system.
One method for sensing the current involves reading the voltage across a sensing resistor that is connected in series with the servo motor. The current flowing through the motor is equivalent to that flowing through the resistor. Since the resistor voltage is proportional to the resistor current, it is likewise proportional to the motor current.
A typical bridge structure showing the connections of a prior art servo motor and the series resistor is given in FIG. 1. The circuitry shown forms what is called an "H" bridge. This bridge is formed with two transistors in series between the bridge voltage (VBRIDGE) and ground (GND), the junction of these transistors forming node 1. Another pair of transistors connected in the same fashion form node 2 at their joint connection. The sensing resistor (RS) and the servo motor are connected in series between nodes 1 and 2. By adjusting the gate voltages of transistors T1-T4, the driving currents for the servo motor can be controlled. To sense the current passing through the motor, the voltage across series resistor RS is sampled at node 1 and node 3 as signals SE1 and SE2 respectively. These signals, SE1 and SE2, are provided to a differential amplifier to sense the voltage differential.
Because the motor impedance is inductive, small changes in motor current cause large voltage swings across the motor. The amplifier must be able to sense small differential voltages (on the order of 1-10 millivolts) in the presence of common mode signals that can vary from ground to the bridge voltage (normally a 12 volt range). The goals for such an amplifier are to:
1. Achieve high common mode rejection both at DC and at frequencies approaching 100 kilohertz, PA0 2. Operate accurately with a common mode voltage as high as 13.2 volts while operating from a 5 volt power supply, PA0 3. Provide an output that is referenced to a user supplied input voltage, PA0 4. Provide low output offset, PA0 5. Provide high gain accuracy.
A conventional circuit for a differential amplifier is shown in FIG. 2. The voltage signal SE1 is provided to resistor R1 which is in turn coupled to node 21. Resistor R2 is coupled between node 21 and output node 23. The voltage signal SE2 is provided to resistor R3 which is in turn coupled to node 22. Resistor R4 is coupled between an output reference voltage source and node 22. Node 21 and node 22 are coupled to the negative differential input and positive differential input respectively of the differential amplifier A2. The output of amplifier A2 is coupled to output node 23. The output voltage (V.sub.OUT) is given by: ##EQU1## for resistance values where R1=R3 and R2=R4.
The circuit shown in FIG. 2 has several disadvantages, particularly when fabricated in a CMOS process. For example, if the circuit is designed with a gain of four for the differential inputs, the common mode range of the amplifier must be 4/5 of the common mode input. Thus the circuit cannot handle a common mode input of greater than 6.25 volts and still remain within the 5 volt supply limit. This eliminates the use of high quality amplifiers in this circuit. Also, the common mode rejection of the circuit relies on resistor matching. A 1% resistor mismatch will limit the common mode rejection ratio (CMRR) to 40dB. Another disadvantage is that the circuit operates in continuous time and therefore is not easily auto-zeroed to reduce the effects of amplifier offset.
An alternate prior art differential amplifier utilizes switched capacitor circuitry. One such conventional switched-capacitor circuit for differential amplifiers is shown in FIG. 3. The circuit switches according to control signals AZ and AZ*. These signals represent alternating, non-overlapping timing signals. During the phase when AZ is high, signal SE1 is provided to capacitor C1 which is in turn coupled to the negative input of the differential amplifier A3. The output of amplifier A3 is coupled to the negative input to provide feedback. The positive input of the amplifier is connected to ground. During this phase, node 30 is charged to the value of signal SE1. Since the positive input of the amplifier is grounded and the output of the amplifier is directly coupled to the negative input, the amplifier is auto-zeroed. Capacitor C2 is charged up to the value of the output reference signal.
During the phase when AZ* is high, the direct feedback is cut off and capacitor C2 is connected in a feedback loop. V.sub.OUT receives the stored output reference charge from the capacitor C2. The signal SE2 is provided to capacitor C1 at node 30, thus causing a potential change at the negative input of the amplifier corresponding to the difference between signal SE2 and SE1. The potential change at the negative input of the amplifier also causes a potential change at V.sub.OUT. The potential at V.sub.OUT is given as: E1 ? ##STR1## The valid output for this circuit is available only during the phase when AZ* is high.
This circuit has several advantages over the continuous time version of FIG. 2. The amplifier is auto-zeroed to reduce the offset effects of the amplifier circuitry. Also, the common mode rejection is independent of component tolerances and the operational amplifier can be operated from a 5 volt supply. A disadvantage of this circuit is that the common mode rejection ratio (CMRR) is unacceptable at high frequencies. This is due to the fact that SE1 and SE2 are not sampled at the same time.
A switched capacitor circuit of the prior art that allows for simultaneous sampling of SE1 and SE2 is shown in FIG. 4. In this circuit, signals SE1 and SE2 are each provided to a separate plate of capacitor C3, during the phase when AZ is high. Other than that, the circuit maintains the same structure as that shown in FIG. 3 for the AZ phase. The amplifier has direct negative feedback and is auto-zeroed to a value of 2.5 volts. The capacitor C4 is charged up on one plate to the value of the output reference voltage and on the other plate, to 2.5 volts, where it is coupled to the negative input of the amplifier. The zeroing value of 2.5 volts is used because it lies at the midpoint of the 5 volt supply range. For other supply voltages, the value would be roughly equivalent to the midpoint of the voltage supply. The potential across capacitor C3 is equivalent to the voltage difference between SE2 and SE1.
During the phase when AZ* is high, capacitor C3 is disconnected from the signal lines of SE1 and SE2 and connected to the positive and negative inputs of the amplifier A4. At the same time, the direct feedback is disconnected and the output line is connected to plate 40 of capacitor C4. This charges V.sub.OUT to a potential equal to the output reference voltage. The connection of capacitor C3 to the amplifier inputs triggers a potential change at the negative input that is proportional to the voltage difference SE2-SE1. The redistribution of charge also triggers a voltage change at V.sub.OUT. V.sub.OUT is given by: ##EQU2##
This circuit has the advantages of auto-zeroing, simultaneous sampling, and 5 volt supply operation. However, its common mode rejection ratio is poor because it is sensitive to parasitic capacitances at nodes 41 and 42. These parasitic capacitances serve to capacitively couple nodes 41 and 42 to ground. It is desirable to have an amplifier configuration which provides for a high common mode range that is not limited by the amplifier power supply, common mode rejection that is insensitive to component tolerance, auto-zeroing, and simultaneous sampling. The desired configuration must not be sensitive to parasitic capacitance as is the circuit of FIG. 4.